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Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 16 LVCMOS/LVTTL outputs * 1 LVCMOS/LVTTL clock input * Maximum output frequency: 200MHz * All inputs are 5V tolerant * Output skew: 250ps (maximum) * Part-to-part skew: 800ps (maximum) * Additive phase jitter, RMS: 0.09ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83115 single ended clock input accepts LVCMOS or LVTTL input levels. The ICS83115 operates at full 3.3V supply mode over the commercial temperature range. Guaranteed output and part-topart skew characteristics make the ICS83115 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
OE2 VDD
PIN ASSIGNMENT
4
OE1 Q0 Q1 Q2 VDD VDD Q3 Q4 GND GND Q5 Q6 Q7 IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OE2 Q15 Q14 Q13 VDD VDD Q12 Q11 GND GND Q10 Q9 Q8 OE0
IN
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8
OE2
OE1
ICS83115
28-Lead SSOP, 150mil 9.9mm x 3.9mm x 1.7mm body package R Package (Top View)
4
OE1 GND OE0
83115BR
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REV. A SEPTEMBER 21, 2004
OE0
OE2
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Type Input Pullup Description Output enable. When LOW, forces outputs Q2 thru Q7 to HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3, 4, 7, 8, 11, 12, 13, 16, 17, 18, 21, 22, 25, 26, 27 5, 6, 23, 24 9, 10, 19, 20 14 Name OE1 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 VDD GND IN
Output
LVCMOS/LVTTL clock outputs. 7 typical output impedance.
Power Power Input
Core supply pin. Power supply ground.
Pulldown LVCMOS/LVTTL clock input / 5V tolerant. Output enable. When LOW, forces outputs Q8 thru Q13 to 15 OE0 Input Pullup HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels. Output enable. When LOW, forces outputs Q0, Q1, Q15 and Q14 to 28 OE2 Input Pullup HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN C PD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD = 3.3V 5 Test Conditions Minimum Typical 4 VDD = 3.465V 11 51 51 7 12 Maximum Units pF pF K K
TABLE 3. FUNCTION TABLE
Inputs OE 0 0 0 0 0 1 1 1 1 OE1 0 0 1 1 0 0 1 1 OE2 0 1 0 1 0 1 0 1 Q0, Q1, Q14, Q15 (Control OE2) HiZ Active HiZ Active HiZ Active HiZ Active Outputs Q2:Q7 (Control OE1) HiZ HiZ Active Active HiZ HiZ Active Active Q8:Q13 (Control OE0) HiZ HiZ HiZ HiZ Active Active Active Active
NOTE: OE0:OE2 are 5V tolerant.
83115BR
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REV. A SEPTEMBER 21, 2004
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 49C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0 TO 70C
Symbol VDD IDD Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 50 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0 TO 70C
Symbol Parameter VIH VIL IIH IIL VOH VOL IOZL IOZH Input High Voltage Input Low Voltage Input High Current Input Low Current OE0:OE2 IN OE0:OE2 IN OE0:OE2 IN OE0:OE2 IN VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 2.6 0.5 5 5 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V A A
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output HiZ Current Low Output HiZ Current High
NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
83115BR
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REV. A SEPTEMBER 21, 2004
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions 200MHz Integration Range: 12KHz - 20MHz Measured on rising edge @VDD/2 Measured on rising edge @VDD/2 20% to 80% 650 45 Minimum 1.7 Typical 2.4 0.09 150 250 800 1150 55 20 20 Maximum 200 3.1 Units MHz ns ps ps ps ps % ns ns
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0 TO 70C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time Output Disable Time
t jit(O) t sk(o) t sk(pp)
tR / tF odc tEN tDIS
All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83115BR
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REV. A SEPTEMBER 21, 2004
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz) = 0.09ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
83115BR
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REV. A SEPTEMBER 21, 2004
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5%
VDD
SCOPE
Qx
VDD 2
LVCMOS
GND
Qx
VDD 2
Qy
tsk(b)
-1.65V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Part 1
Qx
V
DD
2
CLK
VDD 2
Part 2
Qy
V
DD
2 tsk(pp)
Q0:Q15
VDD 2 t
PD
PART-TO-PART SKEW
PROPAGATION DELAY
V
DD
80% 20% tR
80%
Q0:Q15 Pulse Width
2
Clock Outputs
20% tF
odc =
t
PERIOD
t PW t PERIOD
OUTPUT RISE/FALL TIME
83115BR
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A SEPTEMBER 21, 2004
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
28 LEAD SSOP, 150MIL
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. 49C/W
200
36C/W
500
30C/W
TRANSISTOR COUNT
The transistor count for ICS83115 is: 985
83115BR
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REV. A SEPTEMBER 21, 2004
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
28 LEAD SSOP, 150 MIL
PACKAGE OUTLINE - R SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L ZD 0.40 0 0.84 REF 0.20 0.18 9.80 5.80 3.80 0.635 BASIC 1.27 8 1.35 0.10 Millimeters Minimum 28 1.75 0.25 1.50 0.30 0.25 10.00 6.20 4.00 Maximum
Reference Document: JEDEC Publication 95, MO-137
83115BR
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REV. A SEPTEMBER 21, 2004
Integrated Circuit Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Package 28 Lead SSOP 28 Lead SSOP on Tape and Reel 28 Lead "Lead Free" SSOP 28 Lead "Lead Free" SSOP on Tape and Reel Count 48 per tube 2500 48 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83115BR ICS83115BRT ICS83115BRLF ICS83115BRLFT Marking ICS83115BR ICS83115BR ICS83115BRLF ICS83115BRLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83115BR
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REV. A SEPTEMBER 21, 2004

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